1. Field of the Invention
The present invention is related generally to semiconductor device testing, and specifically to testing the program and erase functions of a floating gate cell within a programmable device element.
2. Description of the Background Art
Semiconductor devices are typically fabricated in large lots on silicon wafers. The fabrication process includes various steps such as deposition, electron beam lithography, plasma etching, sputtering and other techniques well known to those skilled in the art of semiconductor fabrication. As with any manufacturing process, defects arise during semiconductor fabrication. These defects must be detected by the manufacturer before devices are delivered to customers.
In complex programmable logic devices (CPLDs, also known as erasable PLDs or EPLDs), floating gate elements are used to store a designed configuration. Floating gate element 5 is illustrated in FIG. 1 within a programmable EEPROM cell and in FIG. 2 within a CPLD FastFLASH.TM. transistor found in CPLDs available from Xilinx, Inc., the assignee of the present invention. For presently available Xilinx CPLDs, the normal test flow includes first programming the cell, then verifying that the cell was programmed sufficiently (that the cell is "off" and stable in its "off" state) by applying a predetermined reference voltage to control gate element 7 and checking for the expected "off" reading. The cell is then erased (set to an "on" state) and the erase function is similarly verified. The test flow then continues to test additional functions.
Thus, program and erase functionality of CPLDs is verified by applying a reference voltage to control gate 7 and verifying the transistor state. If the reference voltage level applied to the cell terminals provides the expected state of the cell at a designated point in time, then the cell passes the test and the test flow continues. If not, then according to the available testing method additional programming pulses are applied until a predetermined time period has passed. If the device still has not reached the desired state, the device fails.
There is, therefore, a weakness in the available testing method for program and erase functionality of floating gate elements: the length of time needed to determine whether a device is properly programmed or erased is inversely proportional to the device's measure of functionality. For example, referring to FIG. 3, test curve t1 indicates the response of a fully functional cell at the first program time marker 1 (e.g., the plotted output voltage is greater than a specified 9 volts at time marker 1). In contrast, response curve t2 does not indicate its functionality, and response curves t3 and t4 do not indicate their disfunction, until program time marker 3. Therefore, the testing of an element following any of curves t2, t3, and t4 clearly cannot be reliably accomplished before time marker 3.
The problem is exacerbated where, as with most functional tests, tests are performed with a minimal power supply voltage level to emulate worst-case operating conditions. For floating gate elements under such conditions, program and erase times are especially long, since very little energy is available for electrons to jump on or off floating gate 5 from control gate 7.
Thus, testing flawed or nearly flawed devices to see whether they have programmed or erased under specified operating conditions is especially time-consuming. For in-system programmable (ISP) device testing, where test data is shifted serially first into and then out of the device, there is an even more extreme time problem. Indeed, because of their serial nature, ISP tests can account for thirty percent or more of the overall test time required for a device. There is therefore a need in the art for a floating gate element testing procedure that provides reliable results but is not subject to the long delay periods associated with available methods when applied to devices having borderline pass or fail characteristics.